As I've written many times in this column, the size of transistors within silicon microchips can't continue shrinking forever; at some point, they will reach the molecular scale and disappear down the quantum rabbit hole. That raises all sorts of intriguing possibilities, such as quantum computers (see “Tech Page: Quantum Computing” in the September 1997 issue). However, any practical application of those ideas, including electronic music, is a long way off.
In the meantime, Moore's Law, which states that the density of transistors on a microchip doubles every 18 to 24 months, could soon break down as the pace of miniaturization slows. Historically, the average area of microchips has grown by 15 percent per year, but the Semiconductor Industry Association projects that figure will drop to 4 or 5 percent in the future. In addition, the minimum feature size should decrease by 30 percent every three years instead of every two. Even so, many believe that Moore's Law will exhaust itself in less than 20 years.
Fortunately, there is a way to circumvent that fate. Until now all microchips have been two-dimensional, consisting of a single layer of transistors etched directly onto the surface of silicon crystals. But if multiple silicon layers could be stacked vertically on each other in a three-dimensional configuration, many more transistors could be packed into the same footprint without needing to be any smaller than they are already.
At the forefront of research into 3-D chips is a company called Matrix Semiconductor (www.matrixsemi.com) in California's Silicon Valley. According to cofounder Thomas H. Lee, the key to successfully developing such chips is twofold. First, there must be a way to deposit silicon onto a substrate with individual crystals large enough to hold many transistors. (Silicon with multiple crystals is called polycrystalline silicon or polysilicon.) That technology has been perfected in flat-panel, thin-film transistor (TFT) computer displays, in which a thin film of polysilicon forms regular single-crystal regions (called grains) measuring one micron or more in diameter.
Second, each layer must be extremely uniform in thickness. Matrix has adapted a polishing technique used to make 2-D chips that flattens each layer to within 50 nanometers.
Using those procedures, the company has produced 3-D chips with many layers of polysilicon separated by insulating and connecting and conducting layers. Those chips use conventional materials and fabrication methods, which will reduce manufacturing costs and greatly increase chip densities.
Like any new technology, 3-D chips are not without their limitations. Some transistor elements inevitably straddle the boundary between polysilicon grains, rendering them ineffective and requiring an error correction to route signals around them. Also, thin-film polysilicon transistors typically perform at about half the speed of monocrystalline silicon transistors, though 3-D devices use shorter connections between elements, which helps narrow the speed discrepancy. Finally, heat could be an issue because of the smaller radiating surface area. Still, the technology holds great promise, making solving those problems worth the effort.
Because memory devices are much simpler than microprocessors, Matrix Semiconductor's first commercial product, which should appear later this year under the Thomson brand, is a 3-D memory chip designed to serve as a low-cost medium for digital photography and audio (see Fig. 1). With 512 million memory cells in eight layers, the chip can store several hundred one-megapixel photos or more than an hour of compressed audio. The company has also developed prototypes of more complex 3-D circuits, such as static RAM, EPROM, and logic gates, which will become the basis of 3-D microprocessors and other types of chips on which all digital devices, including musical instruments, depend.